Amorphous-silicon thin film transistors (a-Si TFTs) have been widely used in the display device, for the amorphous-silicon thin film transistors, by using a low-temperature poly-silicon (LTPS) design as the driving assembly can better meet the needs of high-performance and high-resolution for display device in nowadays. At present, in the LTPS process, a channel is usually doped by ion implantation, so as to adjust the threshold voltage, or by using a dopant to reduce the resistance of source electrode/drain electrode. However, with the development of large-size display, the LTPS process, besides its poor uniformity to a large area, the ion implantation can only be currently used in small-size displays. Today, the LTPS technology is sophisticated, the uniformity problem of the thin film is improved, followed by, is how to achieve a source electrode/drain electrode region with low-resistance without using the ion implantation, that is to say, how to define an ohmic contact layer at both ends of the transistor channel, in other words, a non-implant LTPS technology.
FIG. 1 is a flowchart of a method for fabricating a conventional thin film transistor. FIG. 2A˜FIG. 2G are schematic diagrams of a conventional thin film transistor. The flowchart of FIG. 1 is described below, along with FIG. 2A˜FIG. 2G. In step S102 of FIG. 2A, a buffer layer 204 and an amorphous-silicon (a-Si) layer 206 are sequentially disposed on a substrate 202. Next, in step S104 of FIG. 2B, a poly-silicon layer 208 is formed and patterned to define a semiconductor region.
Generally, after the amorphous-silicon layer 206 is formed, the amorphous-silicon layer 206 is converted to the poly-silicon layer 208 having a polycrystalline structure by a low temperature crystallization process. In step S106 of FIG. 2C, an ohmic contact layer 210 is formed on the poly-silicon layer 208 and patterned to define a channel region 212, further the ohmic contact layer 210 of the channel region 212 is etched by a dry etching manner.
A N+ or a P+ layer is being grown on the poly-silicon as the ohmic contact layer 210 by chemical vapor deposition, the thickness of the ohmic contact layer is generally between 400-800 Å, after that, the channel region 212 is defined by using a mask, and then the ohmic contact layer 210 of the channel region is etched. However, in this step, the uniformity issue of the dry etching manner will cause a partial region of the ohmic contact layer 210 insufficient etched, and some regions are over etched to the poly-silicon layer 208, so that the thickness of the poly-silicon layer 208 is reduced, causing the electrical uniformity of the thin film of the LCD panel performing poor, thus making the panel mura a more serious problem.
Next, in step S108 of FIG. 2D, a gate insulating layer 214 is formed on the ohmic contact layer 210 and the poly-silicon layer 208, so that the gate insulating layer 214 covers the channel region 212 and the ohmic contact layer 210. In step S110 2E of FIG. 2E, a gate electrode 216 is formed on the gate insulating layer 214. In step S112 of FIG. 2F, a dielectric layer 218 is formed on the gate electrode 216 and the gate insulating layer 214, as well as formed through holes 220. The through holes 220 are located on two sides of the gate electrode 216, respectively, and pass through the dielectric layer 218 and the gate insulating layer 214 to expose the ohmic contact layer 210. Finally, in step S114 of FIG. 2G, a source electrode and a drain electrode 222 are formed on the through holes 220.
As described above, the non-implant LTPS technology needs to improve the uneven thickness problems of the poly-silicon layer 208 caused by the dry etching of the ohmic contact layer 210. Generally, the ohmic contact layer is deposited after the poly-silicon layer 208 is formed, after the channel region 212 is defined by using the mask, and the ohmic contact layer 210 of the channel region 212 is etched by the dry etching manner, only contact regions of the source electrode and the drain electrode are left. Since the thickness of the ohmic contact layer 210 is generally thin, which is between 300 Å-800 Å, the thickness of the poly-silicon layer 208 is around 400 Å-800 Å. Therefore, in the etching process of the ohmic contact layer 210, an over etched to the poly-silicon layer 208 is inevitable.
In addition, due to the uniformity problems of etching machine, some areas are more etched, while some areas are less etched, the more etched areas are likely to cause electrical changes of the thin film transistor, and the less etched areas will increase electricity leakage, and seriously cause a short circuit.
Thus, a novel method for fabricating a thin film transistor is needed, through altering the manufacturing processes, and breaking the limitation of the channel region, so as to improve the over etching to the poly-silicon layer or the insufficient etching of the ohmic contact layer when etching the ohmic contact layer, and overcome the etching uniformity and accuracy problems caused by etching the ohmic contact layer.